The performance improvement of processors that process digital information has contributed to the recent development of digital technology. The performance of processors used in servers and PCs are evaluated based on the processing speed and the processing capability within a given time period. Meanwhile, one of the important performance indicators for embedded processors used in mobile information devices and digital home appliances is how well it processes interrupts. For instance, in order to add various functions to a mobile phone or electronically control a car, not only the processing performance of the processor core needs to be high, but also special-purpose circuits that perform particular processings are provided on-chip or off-chip around the processor core in addition to other peripheral circuits such as a timer. Normally, interrupt signals are used by these circuits to notify the processor core of completion or abnormality of processing. Since an increase in the number of peripheral circuits of the processor core means increase in the number of interrupts, an interrupt controller that manages interrupt requests from the peripheral circuits and that notifies appropriate requests to the processor core is provided between the processor core and the peripheral circuits. For embedded processors, the performance of this interrupt controller is also important.
One of the performance indicators for the interrupt controller is the number of interrupts that it can receive. The sources of interrupts, such as the aforementioned special-purpose circuits and multiprocessor cores in addition to DMACs (Direct Memory Access Controllers), timers, and serial interfaces, have increased and diversified. An efficient device is required to process a large number of interrupts generated by these sources of interrupts as the number of connected channels increases.
The interrupt controller notifies the occurrence of an interrupt to the processor core. There is a time lag from the moment when an interrupt occurs until the processor core starts processing in response to the interrupt, and a plurality of interrupts may occur during the time lag. Since the processor core can process only one interrupt at a time, when a plurality of interrupts occur, the interrupt controller selects an appropriate one from these multiple interrupt factors and notifies the processor core. As the determination reference for selecting an appropriate interrupt factor, an interrupt priority level is assigned to each interrupt factor. Two general types of priority level are as follows.
The first type is a fixed priority level determined at the time of designing the circuit. For the sake of management, a number is assigned to each input port receiving an interrupt from an external factor, and a circuit that selects interrupts in the ascending order of the port number (smaller numbers have higher priority levels) is provided in this first method. For example, when ports 3 and 7 receive interrupts simultaneously, the port 3, the smaller number, is always selected. Since the priority levels are determined when designing the circuit, the order in which the peripheral circuits are connected to the ports is important. Depending on the product in which the device is used, it is necessary to change the connection order, therefore this method lacks flexibility. On the other hand, it has an advantage that the selection circuit can be easily constituted since the circuit simply has to select in the ascending order of the port number even when a plurality of interrupts occur. The circuit delay of the selection circuit depends only on the number of interrupt factors connected. We will call this first type of priority level “fixed priority level.”
The second type is a variable priority level that can be changed after the circuit has been designed. Memory means such as a register that holds a priority level value is provided for each input port. When one factor is selected from a plurality of interrupt factors, these priority level values are compared and a factor with the highest priority level is selected. The priority level values are set by software when the product is being used and can be changed as necessary. Therefore, this method has an advantage of being flexible since much consideration does not have to be given to the order in which the peripheral circuits are connected to the input ports and appropriate priority levels can be assigned to the peripheral circuits for each product to which the device is applied. On the other hand, it has a disadvantage that the selection circuit becomes very complex because it has to select a factor with the highest priority level from a large number of interrupt factors. The circuit delay of the selection circuit depends on the number of settable interrupt priority levels, in addition to the number of interrupt factors connected. We will call this second type of priority level “variable priority level.” An example of interrupt processing using variable priority levels is disclosed in Japanese Patent Kokai Publication No. JP-A-11-149382(hereinafter Patent Document 1).
Many interrupt controllers use both the types of priority levels. For instance, once interrupts are received, variable priority levels are compared first, and an interrupt factor is selected. Further, when the same priority level value is set to more than one port, an interrupt factor is selected according to fixed priority levels. In other words, the priority order is determined according to the two types of priority levels.
Next, the variable priority level disclosed in Patent Document 1 will be described, focusing only on the main part relating to the present invention. FIG. 13 is a drawing illustrating the configuration of an interrupt controller disclosed in Patent Document 1. The interrupt controller 100 is shown to have only one interrupt input port 200, however, it can support a large number of interrupt inputs by providing as many configurations shown in FIG. 13 as the number of interrupt factors necessary. When an interrupt is received through the port 200, the interrupt controller 100 outputs it from a port 201. The output from the port 201 is the logic OR of all interrupts received through the ports, and first, the processor core is notified that the interrupt has been received. The processor core that has received the interrupt request returns an acknowledgement to the interrupt controller 100 when it is ready to receive the interrupt and start interrupt processing. The interrupt controller 100 that has received the acknowledgement opens the output gate of an ABT-BUS transceiver 108, and outputs priority levels held in a register 106 to an ABT-BUS 204. The output of the ABT-BUS transceiver 108 is an open collector output that has a high impedance when the bit value of the register 106 is 1 and that is at low level when the bit value is 0. After a given time period such as one clock cycle has passed, an arbitration bit comparator 109 compares the value of the ABT-BUS 204 and the value of its priority level register 106 from the most significant bit to the least significant bit at a rate of one bit per clock cycle.
The ABT-BUS 204 is at a high impedance state when the value of the register is 1. When another interrupt controller connected to the ABT-BUS 204 is outputting 0, the comparison result is “nonidentical” since A is 1 and B is 0. When a smaller value of the priority level register has a higher priority, “nonidentical” means that an interrupt with a higher priority level than the one that the interrupt controller 100 has received exists. In this case, the bit comparison thereafter is suspended, and the output gate of the ABT-BUS transceiver 108 is closed. The arbitration bit comparator 109 continues to compare the priority levels of the other ports with its own as described above and when there are values confirmed to be identical from the most significant bit to the least significant bit, an arbitration control unit 110 determines that its request has the highest priority level and that it is qualified to notify the request to the processor core. Then, a gate 105 is opened and the value of an interrupt vector register 103 is outputted to a DATA terminal 203. The processor core receives the interrupt vector outputted to the DATA terminal 203, and moves on to interrupt processing.